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data book 1 1.00 hys 72vxx3xxgr-7.5 pc133 registered sdram-modules 3.3 v 168-pin registered sdram modules pc133 128 mbyte module pc133 256 mbyte module pc133 512 mbyte module pc133 1 gbyte module the hys 72vxx3xxgr-7.5 are industry standard 168-pin 8-byte dual in-line memory modules (dimms) organized as 16m 72, 32m x 72, 64m 72 and 128m 72 high speed memory arrays designed with synchronous drams (sdrams) for ecc applications. the 32m x 72 (256mbyte) registered dimm module is available in two versions (12 or 13 row addresses). all control and address signals are registered on-dimm and the design incorporates a pll circuit for the clock inputs. use of an on-board register reduces capacitive loading on the input signals but are delayed by one cycle in arriving at the sdram devices. decoupling capacitors are mounted on the pc board. the dimms use a serial presence detects scheme implemented via a serial e 2 prom using the 2-pin i 2 c protocol. the first 128 bytes are utilized by the dimm manufacturer and the second 128 bytes are available to the end user. all infineon 168-pin dimms provide a high performance, flexible 8-byte interface in a 133.35 mm long footprint. ? 168-pin registered 8 byte dual-in-line sdram module for pc and server main memory applications ? one bank 16m 72, 32m x 72 and 64m 72 two bank 128m 72 organization ? optimized for ecc applications with very low input capacitances ? jedec standard synchronous drams (sdram) programmable cas latency, burst length and wrap sequence (sequential & interleave) ? single + 3.3 v ( 0.3 v) power supply ? programmable cas latency, burst length, and wrap sequence (sequential & interleave) ? auto refresh (cbr) and self refresh ? all inputs and outputs are lvttl compatible ? serial presence detect with e 2 prom ? utilizes sdrams in tsopii-54 packages with registers and pll. ? card size: 133.35 mm 43.18 mm 3.99/ 8.13 mm with gold contact pads (jedec mo-161) ? these modules all fully compatible with the current industry standard pc133 specifications ? performance: -7.5 unit f ck clock frequency (max.) @ cl = 3 133 mhz t ck clock cycle time (min.) @ cl = 3 7.5 ns t ac clock access time (min.) cas latency = 3 5.4 ns
hys 72vxx3xxgr-7.5 pc133 registered sdram-modules data book 2 1.00 note: hys 72v32301gr-7.5 all part numbers end with a place code (not shown), designating the die revision. consult factory for current revision. example: hys 64v16300gr-7.5-c2, indicating rev.c2 dies are used for sdram components. ordering information type compliance code description sdram technology hys 72v16300gr-7.5 pc133r-333-542-b2 one bank 128 mb reg. dimm 64 mbit hys 72v16301gr-7.5 pc133r-333-542-b2 one bank 128 mb reg. dimm 128 mbit hys 72v32301gr-7.5 pc133r-333-542-b2 one bank 256 mb reg. dimm 128 mbit hys 72v32300gr-7.5 pc133r-333-542-aa one bank 256 mb reg. dimm 256 mbit hys 72v64300gr-7.5 pc133r-333-542-b2 one bank 512 mb reg. dimm 256 mbit hys 72v128320gr-7.5 pc133r-333-542-b2 two banks 1 gbyte reg. dimm 256 mbit (stacked) pin definitions and functions a0 - a11, a12 address inputs (a12 is used for 256mbit based modules only) dqmb0 - dqmb7 data mask ba0, ba1 bank selects cs0 - cs3 chip select dq0 - dq63 data input/output rege register enable cb0 - cb7 check bits v dd power (+ 3.3 v) ras row address strobe v ss ground cas column address strobe scl clock for presence detect we read/write input sda serial data out cke0 clock enable n.c. no connection clk0 - clk3 clock input CC address format density organization memory banks sdrams # of sdrams # of row/bank/ columns bits refresh period interval 128 mb 16m 72 1 16m 4 18 12/2/10 4k 64 ms 15.6 m s 128 mb 16m 72 1 16m x 8 9 12/2/10 4k 64 ms 15.6 m s 256 mb 32m x 72 1 32m x 4 18 12/2/11 4k 64 ms 15.6 m s 256 mb 32m x 72 1 32m x 8 9 13/2/10 8k 64 ms 7.8 m s 512 mb 64m 72 1 64m 4 18 13/2/11 8k 64 ms 7.8 m s 1 gb 128m 72 2 64m 4 36 13/2/11 8k 64 ms 7.8 m s
hys 72vxx3xxgr-7.5 pc133 registered sdram-modules data book 3 1.00 pin configuration pin# symbol pin# symbol pin# symbol pin# symbol 1 v ss 43 v ss 85 v ss 127 v ss 2 dq0 44 du 86 dq32 128 cke0 3dq1 45cs2 87 dq33 129 cs3 4 dq2 46 dqmb2 88 dq34 130 dqmb6 5 dq3 47 dqmb3 89 dq35 131 dqmb7 6 v dd 48 du 90 v dd 132 n.c. 7dq4 49 v dd 91 dq36 133 v dd 8 dq5 50 n.c. 92 dq37 134 n.c. 9 dq6 51 n.c. 93 dq38 135 n.c. 10 dq7 52 cb2 94 dq39 136 cb6 11 dq8 53 cb3 95 dq40 137 cb7 12 v ss 54 v ss 96 v ss 138 v ss 13 dq9 55 dq16 97 dq41 139 dq48 14 dq10 56 dq17 98 dq42 140 dq49 15 dq11 57 dq18 99 dq43 141 dq50 16 dq12 58 dq19 100 dq44 142 dq51 17 dq13 59 v dd 101 dq45 143 v dd 18 v dd 60 dq20 102 v dd 144 dq52 19 dq14 61 n.c. 103 dq46 145 n.c. 20 dq15 62 du 104 dq47 146 du 21 cb0 63 n.c. 105 cb4 147 rege 22 cb1 64 v ss 106 cb5 148 v ss 23 v ss 65 dq21 107 v ss 149 dq53 24 n.c. 66 dq22 108 n.c. 150 dq54 25 n.c. 67 dq23 109 n.c. 151 dq55 26 v dd 68 v ss 110 v dd 152 v ss 27 we 69 dq24 111 cas 153 dq56 28 dqmb0 70 dq25 112 dqmb4 154 dq57 29 dqmb1 71 dq26 113 dqmb5 155 dq58 30 cs0 72 dq27 114 cs1 156 dq59 31 du 73 v dd 115 ras 157 v dd 32 v ss 74 dq28 116 v ss 158 dq60 33 a0 75 dq29 117 a1 159 dq61
hys 72vxx3xxgr-7.5 pc133 registered sdram-modules data book 4 1.00 34 a2 76 dq30 118 a3 160 dq62 35 a4 77 dq31 119 a5 161 dq63 36 a6 78 v ss 120 a7 162 v ss 37 a8 79 clk2 121 a9 163 clk3 38 a10 (ap) 80 n.c. 122 ba0 164 n.c. 39 ba1 81 wp 123 a11 165 sa0 40 v dd 82 sda 124 v dd 166 sa1 41 v dd 83 scl 125 clk1 167 sa2 42 clk0 84 v dd 126 a12 168 v dd pin configuration (contd) pin# symbol pin# symbol pin# symbol pin# symbol
hys 72vxx3xxgr-7.5 pc133 registered sdram-modules data book 5 1.00 block diagram: one bank 16m 72, 32m 72 and 64m 72 sdram dimm modules hys72v16300gr, hys72v32301gr and hys 72v64300gr using x4 organized sdrams spb04135 dqm dq0-dq3 cs d0 dqm dq0-dq3 d1 dqm dq0-dq3 d2 dqm dq0-dq3 d3 dqm dq0-dq3 d16 dq0-dq3 dq4-dq7 rdqmb1 dq8-dq11 dq12-dq15 cb0-cb3 rdqmb0 rcs0 dqm dq0-dq3 d8 dqm dq0-dq3 d9 dqm dq0-dq3 d10 dqm dq0-dq3 d11 dqm dq0-dq3 d17 dq32-dq35 dq36-dq39 rdqmb5 dq40-dq43 dq44-dq47 cb4-cb7 rdqmb4 dqm dq0-dq3 d4 dqm dq0-dq3 d5 dqm dq0-dq3 d6 dqm dq0-dq3 d7 dq16-dq19 dq20-dq23 rdqmb3 dq24-dq27 dq28-dq31 rdqmb2 rcs2 dqm dq0-dq3 d12 dqm dq0-dq3 d13 dqm dq0-dq3 d14 dqm dq0-dq3 d15 dq48-dq51 dq52-dq55 rdqmb7 dq56-dq59 dq60-dq63 rdqmb6 clk0 12 pf pll sdrams d0-d17 clk1, clk2, clk3 12 pf register cs0/cs2 dqmb0-7 ba0, ba1 a0-a11, a12 ras cas cke0 we rcs0/rcs2 rdqmb0-7 rba0, rba1 ra0-ra11, ra12 rras rcas rcke0 rwe rege 10 k w sdrams d0-d17 sdrams d0-d17 sdrams d0-d17 sdrams d0-d17 sdrams d0-d17 sdrams d0-d17 sa0 sda sa0 sa1 sa1 sa2 sa2 scl scl wp 47 k w e 2 prom (256 word x 8 bit) v cc v ss c d0-d17, reg., dll d0-d17, reg., dll 1) dq wirding may differ from that decribed in this drawing; however dq/dqb relationship must be maintained as shown 2) all resistors are 10 w unless otherwise noted v cc cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs
hys 72vxx3xxgr-7.5 pc133 registered sdram-modules data book 6 1.00 block diagram: one bank 16mx72 and 32m 72 modules hys72v16301 & hys72v32300gr using x8 organized sdrams spb04130 dq0-dq7 cs d0 dq0-dq7 rdqmb0 rcs0 dq0-dq7 cs d4 dq32-dq39 clk0 12 pf pll sdrams d0-d8 clk1, clk2, clk3 12 pf register cs0/cs2 dqmb0-7 ba0, ba1 a0-a11,12* ) ras cas cke0 we rcs0/rcs2 rdqmb0-7 rba0, rba1 ra0-11,12 rras rcas rcke0 rwe rege 10 k w sdrams d0-d8 sdrams d0-d8 sdrams d0-d8 sdrams d0-d8 sdrams d0-d8 sdrams d0-d8 sa0 sda sa0 sa1 sa1 sa2 sa2 scl scl wp 47 k w e 2 prom (256 word x 8 bit) v cc v ss c d0-d8, reg., dll d0-d8, reg., dll notes: 1) dq wirding may differ from that decribed in this drawing; however dq/dqb relationship must be maintained as shown 2) all resistors are 10 w unless otherwise noted * ) a12 is only for 32 m x 72 organisation v cc dqm rdqmb4 dqm dq0-dq7 cs d1 dq8-dq15 rdqmb1 dq0-dq7 cs d5 dq40-dq47 dqm rdqmb5 dqm dq0-dq7 cs d8 rcb0-rcb7 dqm we dq0-dq7 cs d2 dq16-dq23 rdqmb2 rcs2 dq0-dq7 cs d6 dq48-dq55 dqm rdqmb4 dqm dq0-dq7 cs d3 dq24-dq31 rdqmb3 dq0-dq7 cs d7 dq56-dq63 dqm rdqmb7 dqm
hys 72vxx3xxgr-7.5 pc133 registered sdram-modules data book 7 1.00 block diagram: two bank 128m 72 sdram dimm modules hys 72v128320gr using stacked x4 organized sdrams spb04136 dqm dq0-dq3 d0 dqm dq0-dq3 d0 dqm dq0-dq3 d1 dqm dq0-dq3 d1 dqm dq0-dq3 d2 dqm dq0-dq3 d2 dqm dq0-dq3 d3 dqm dq0-dq3 d3 dqm dq0-dq3 d16 dqm dq0-dq3 d16 dq0-dq3 dq4-dq7 rdqmb1 dq8-dq11 dq12-dq15 cb0-cb3 rdqmb0 rcs1 rcs0 dqm dq0-dq3 d8 dqm dq0-dq3 d8 dqm dq0-dq3 d9 dqm dq0-dq3 d9 dqm dq0-dq3 d10 dqm dq0-dq3 d10 dqm dq0-dq3 d11 dqm dq0-dq3 d11 dqm dq0-dq3 d17 dqm dq0-dq3 d17 dq32-dq35 dq36-dq39 rdqmb5 dq40-dq43 dq44-dq47 cb4-cb7 rdqmb4 dqm dq0-dq3 d4 dqm dq0-dq3 d4 dqm dq0-dq3 d5 dqm dq0-dq3 d5 dqm dq0-dq3 d6 dqm dq0-dq3 d6 dqm dq0-dq3 d7 dqm dq0-dq3 d7 dq16-dq19 dq20-dq23 rdqmb3 dq24-dq27 dq28-dq31 rdqmb2 rcs3 rcs2 dqm dq0-dq3 d12 dqm dq0-dq3 d12 dqm dq0-dq3 d13 dqm dq0-dq3 d13 dqm dq0-dq3 d14 dqm dq0-dq3 d14 dqm dq0-dq3 d15 dqm dq0-dq3 d15 dq48-dq51 dq52-dq55 rdqmb7 dq56-dq59 dq61-dq63 rdqmb6 clk0 12 pf pll stacked sdrams d0-d17 clk1, clk2, clk3 12 pf register cs0-cs3 dqmb0-7 ba0, ba1 a0-a11, a12* ) ras cas cke0 we rcs0-rcs3 rdqmb0-7 rba0, rba1 ra0-ra11 rras rcas rcke0 rwe rege 10 k w stacked sdrams d0-d17 stacked sdrams d0-d17 stacked sdrams d0-d17 stacked sdrams d0-d17 stacked sdrams d0-d17 stacked sdrams d0-d17 * ) a12 is only used for 128 m x 72 organisation sa0 sda sa0 sa1 sa1 sa2 sa2 scl scl wp e 2 prom (256 word x 8 bit) v cc v ss c d0-d17, reg. dll d0-d17, reg. dll 1.) dq wirding may differ from that decribed in this drawing; however dq/dqb relationship must be maintained as shown 2.) all resistors are 10 w unless otherwise noted v cc 47 k w cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs
hys 72vxx3xxgr-7.5 pc133 registered sdram-modules data book 8 1.00 dc characteristics t a = 0 to 70 c 1) ; v ss =0v; v dd , v ddq =3.3v 0.3 v parameter symbol limit values unit min. max. input high voltage v ih 2.0 v dd +0.3 v input low voltage v il C0.5 0.8 v output high voltage ( i out =C4.0ma) v oh 2.4 C v output low voltage ( i out = 4.0 ma) v ol C0.4v input leakage current, any input (0 v < v in < 3.6 v, all other inputs = 0 v) i i(l) C10 10 m a output leakage current (dq is disabled, 0 v < v out < v dd ) i o(l) C10 10 m a capacitance t a = 0 to 70 c 1) ; v dd =3.3v 0.3 v, f =1mhz parameter symbol limit values (max.) unit one bank modules two bank modules input capacitance (all inputs except clk and cke) c in 10 20 pf input capacitance (clk) c clk 30 30 pf input capacitance (cke) c cke 17 30 pf input/output capacitance (dq0 - dq63, cb0 - cb7) c io 10 17 pf input capacitance (scl, sa0 - 2) c sc 88pf input/output capacitance (sda) c sd 88pf
hys 72vxx3xxgr-7.5 pc133 registered sdram-modules data book 9 1.00 operating currents per sdram component t a = 0 to 70 c 1) , v dd =3.3v 0.3 v (recommended operating conditions unless otherwise noted) parameter test condition symbol 64 mb 128 mb 256 m b unit note max. operating current t rc = t rc(min.) , t ck = t ck(min.) outputs open, burst length = 4, cl = 3 all banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access C i cc1 x4 100 120 270 ma 2) precharge stand-by current in power down mode cs = v ih(min.) , cke v il(max.) t ck =min. i cc2p 222ma 2) precharge stand-by current in non-power down mode cs = v ih (min.) , cke 3 v ih(min.) t ck =min. i cc2n 35 40 35 ma 2) no operating current t ck = min., cs = v ih(min.) , active state (max. 4 banks) cke 3 v ih(min.) i cc3n 45 50 50 ma 2) cke v il(max.) i cc3p 81010ma 2) burst operating current t ck =min., read command cycling C i cc4 x4 60 120 270 ma 2), 3) auto refresh current t ck =min., auto refresh command cycling C i cc5 130 180 240 ma 2) self refresh current self refresh mode, cke = 0.2 v C i cc6 11.52.5ma 2)
hys 72vxx3xxgr-7.5 pc133 registered sdram-modules data book 10 1.00 ac characteristics (sdram device specification) 4), 5) t a = 0 to 70 c 1) ; v ss =0v; v dd =3.3v 0.3 v, t t =1ns parameter symbol limit values unit note -7.5 min. max. clock and access time clock cycle time cas latency = 3 cas latency = 2 (64mb & 128mb based mod.) cas latency = 2 (256mb based modules) t ck 7.5 10 12 C C C ns ns ns C clock frequency cas latency = 3 cas latency = 2 (64mb & 128mb based mod.) cas latency = 2 (256mb based modules) f ck C C C 133 100 83 mhz mhz mhz C access time from clock cas latency = 3 cas latency = 2 t ac C C 5.4 6 ns ns C clock high pulse width t ch 2.5 C ns C clock low pulse width t cl 2.5 C ns C transition time t t 0.5 10 ns C setup and hold parameters input setup time t is 1.5 C ns C input hold time t ih 0.8 C ns C power down mode entry time t sb C1clkC power down mode exit setup time t pde 1CclkC mode register setup time t rcs 2CclkC common parameters row to column delay time t rcd 20 C ns C row precharge time t rp 20 C ns C row active time t ras 45 100k ns C row cycle time t rc 67.5 C ns C activate (a) to activate (b) command period t rrd 2CclkC cas (a) to cas (b) command period t ccd 1CclkC
hys 72vxx3xxgr-7.5 pc133 registered sdram-modules data book 11 1.00 refresh cycle refresh period 64&128mbit sdram based modules 256 mbit sdram based modules t ref C C 15.6 7.8 m s m s C self refresh exit time t srex 1Cclk 6) read cycle data out hold time t oh 3CnsC data out to low impedance time t lz 0Cns 7) data out to high impedance time t hz 37ns 7) dqm data out disable latency t dqz C2clkC write cycle data input to precharge (write recovery) t wr 2CclkC dqm write mask latency t dqw 0CclkC ac characteristics (sdram device specification) (contd) 4), 5) t a = 0 to 70 c 1) ; v ss =0v; v dd =3.3v 0.3 v, t t =1ns parameter symbol limit values unit note -7.5 min. max.
hys 72vxx3xxgr-7.5 pc133 registered sdram-modules data book 12 1.00 notes 1. the registered dimm modules are designed to operate under system operating conditions between 0-55 deg c ambient, maximum sustained bandwidth and 0 lfm airflow. 2. these parameters depend on the cycle rate. all values are measured at 133 mhz operation frequency. input signals are changed once during tck excepts for icc6 and for standby currents when tck = infinity. 3. these parameters are measured with continous data stream during read access and all dq toggling. cl=3 and bl=4 is assumed and the vcc current is excluded. 4. an initial pause of 100 m s is required after power-up. then a precharge all banks command must be given followed by eight auto refresh (cbr) cycles before the mode register set operation can begin. also the on-dimm pll must be given enough clock cycles to stabilize ( t stab ) before any operation can be guaranteed. 5. ac timing tests have v il = 0.8 v and v ih = 2.0 v with the timing referenced to the 1.4 v crossover point. the transition time is measured between v ih and v il . all ac measurements assume t t = 1 ns with the ac output load circuit shown. specified t ac and t oh parameters are measured with a 50 pf only, without any resistive termination and with a input signal of 1 v/ns edge rate between 0.8 v and 2.0 v. 6. self refresh exit is a synchronous operation and begins on the second positive clock edge after cke returns high. self refresh exit is not complete until a time period equal to t rc is satisfied after the self refresh exit command is registered. 7. referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. a serial presence detect storage device - e 2 prom 34c02 - is assembled onto the module. information about the module configuration, speed, etc. is written into the e 2 prom device during module production using a serial presence detect protocol (i 2 c synchronous 2-wire bus). 50 pf i/o measurement conditions for t ac and t oh spt03404 clock 2.4 v 0.4 v input hold t setup t t t output 1.4 v t lz ac t t ac oh t hz t 1.4 v cl t ch t
hys 72vxx3xxgr-7.5 pc133 registered sdram-modules data book 13 1.00 spd-table for -7.5 registered dimm modules with pll byte# description spd entry value hex 128 mb 1 bank 1) 128 mb 1 bank 2) 256 mb 1 bank*) 256 mb 1 bank**) 512 mb 1bank 1gb 2 banks 0 number of spd bytes 128 80 1 total bytes in serial pd 256 08 2 memory type sdram 04 3 number of row addresses (without bs bits) 12/13 0c 0c 0c 0d 0d 0d 4 number of column addresses 10/11 0a 0a 0b 0a 0b 0b 5 number of dimm banks 1/2 01 01 01 01 01 02 6 module data width 72 48 7 module data width (contd) 0 00 8 module interface levels lvttl 01 9 cycle time at cl = 3 7.5 ns 75 10 access time from clock at cl = 3 5.4 ns 54 11 dimm config (error det/corr.) ecc 02 12 refresh rate/type 15.6/7.8 m s 808080828282 13 sdram width, primary x4 / x8 04 08 04 08 04 04 14 error checking sdram data width x4 / x8 04 08 04 08 04 04 15 minimum t ccd 1 clk 01 16 burst length supported 1, 2, 4, 8 & (full page) 8f 0f 0f 0f 0f 0f 17 number of sdram banks 4 04 18 sdram supported cas latencies 2 & 3 06 19 sdram cs latencies 0 01 20 sdram we latencies 0 01 21 sdram dimm module attributes with pll 1f 22 sdram device attributes v dd tol +/C 10% 0e 23 min. clock cycle time at cl = 2 10/12 ns a0 a0 a0 c0 c0 c0 24 max. data access time from clock for cl = 2 6.0 606060606060 25 min. clock cycle time at cl = 1 not supported 00 26 max. data access time from clock at cl = 1 not supp. 00
hys 72vxx3xxgr-7.5 pc133 registered sdram-modules data book 14 1.00 1) hys72v16300gr-7.5 2) hys72v16301gr-7.5 *) hys72v32301gr-7.5 **) hys72v32300gr-7.5 27 sdram minimum t rp 20 ns 14 28 sdram minimum t rrd 15 ns 0f 29 sdram minimum t rcd 20 ns 14 30 sdram minimum t ras 45 ns 2d 31 module bank density (per bank) 128 mbyte/ 256 mbyte 512 mbyte 20 20 40 40 80 80 32 sdram input setup time 1.5 ns 15 33 sdram input hold time 0.8 ns 08 34 sdram data input setup time 1.5 ns 15 35 sdram data input hold time 0.8 ns 08 36-61 superset information (may be used in future) C00 62 spd revision jedec 2 02 63 checksum for bytes 0 - 62 C c8 50 69 93 cc cd 64-125 manufacturers information C 126 frequency specification C 64 127 details of clocks C 8f 8f 8f 8d 8d 8d 128+ unused storage locations C ff ff ff ff ff ff spd-table for -7.5 registered dimm modules with pll (contd) byte# description spd entry value hex 128 mb 1 bank 1) 128 mb 1 bank 2) 256 mb 1 bank*) 256 mb 1 bank**) 512 mb 1bank 1gb 2 banks
hys 72vxx3xxgr-7.5 pc133 registered sdram-modules data book 15 1.00 package outlines module package jedec mo-161 registered dimm modules raw card aa l-dim168-44 256mb modules 3.99 0.157 max. side 1.27 0.10 0.050 0.004 4.24 0.167 4.24 0.167 front back front 1.5" (nominal) note: all outline dimensions and tolerances are in accordance with the jedec standard
hys 72vxx3xxgr-7.5 pc133 registered sdram-modules data book 16 1.00 package outlines module package jedec mo-161 registered dimm modules raw card b l-dim168-37-2 128mb, 256mb & 512mb modules front 3.99 0.157 max. side 1.27 0.10 0.050 0.004 4.24 0.167 4.24 0.167 front back 1.7" (nominal) note: all outline dimensions and tolerances are in accordance with the jedec standard
hys 72vxx3xxgr-7.5 pc133 registered sdram-modules data book 17 1.00 package outlines module package jedec mo-161 registered dimm modules raw card b l-dim168-37-2 1 gbyte module front 8 max. side 1.27 0.10 0.050 0.004 4.24 0.167 4.24 0.167 front back 1.7" (nominal) note: all outline dimensions and tolerances are in accordance with the jedec standard
hys 72vxx3xxgr-7.5 pc133 registered sdram-modules data book 18 1.00 functional description all these pc133 168-pin registered dimms conform to a compatible set of timing and operation characteristics intended to comply with the 133 mhz standards. the registered dimms achieve high speed data transfer rate up to 133 mhz. all control and address signals are synchronized with the positive edge of externally supplied clocks and are registered on-dimm and hence delayed by one clock cycle in arriving at the sdram devices. the use of the on-board register reduces the capacitive loading of the dimm on input control and address signals. the sdram device data lines (dq) are connected directly to the dimm tabs through 10 ohm series resistors. all the following timing diagrams and explanations show dimm operation at the tabs, not sdram operation. the picture below depicts an overview of the effect of the registered mode on the data outputs (dqs) for a read operation. without the registers, the data is delayed according to the device cas latency, in the case two clocks. with the register, the data is delayed according to the device cas latency plus an additional clock cycle. this is know as the dimm cas latency, and in this example is four three. the data path can be thought of as a pipeline in which the register effectively lengthens the pipe by one clock cycle. in case of a burst write command the data-in is delayed one clock due the op-dimm pipeline register also. therefore, data for the first burst write cycle must be applied on the dq pins on the next clock cycle after the write command is issued. the remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. when the burst has finished, any additional data supplied to the dq pins will be ignored. spt03968 clk read a t0 t1 t2 t3 t4 t5 t6 command dout a0 dout a1 dout a2 dout a3 nop nop nop nop nop cas latency = 2 , dq's ck2 t registered dimm burst read operation (bl = 4) device nop dout a1 dout a0 dout a2 dout a3 cas latency = 3 dimm , dq's ck3 t one clock added for on-dimm pipeline register reg-dimm latency = 1
hys 72vxx3xxgr-7.5 pc133 registered sdram-modules data book 19 1.00 registered dimm burst write operation (bl = 4) dq's the first data element and the write are registered on the next clock edge reg-dimm latency = 1 clk din a0 din a1 extra data is ignored after termination of a burst. don't care din a2 din a3 spt03969 t8 nop clk command nop t0 write a t1 nop t2 nop t3 t6 nop t4 nop t5 t7 nop nop

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